Data buses are used throughout digital computer systems for communicating signals from one portion of the system to another. Digital data buses are used within microprocessor chips to communicate signals between different functional elements included in central processing units ("CPUs") of nticroprocessors or microcomputers, in floating point coprocessor chips, in memory management unit chips, etc. Within a digital computer but outside such integrated circuit chips, digital data buses communicate signals among those chips and between them and other assemblies included within the computer such as Random Access Memories ("RAM"), Read Only Memories ("ROM") and/or peripheral device input/output circuits. External to the computer, digital data buses communicate signals between it and peripheral devices such as keyboards, display devices, printers, modems, disk drives of various different types and/or tape drives.
Because of the widespread use of digital data buses throughout digital computer systems, myriad different types of buses have been developed over the years together with extremely sophisticated protocols governing the signaling process by which data is transferred over the bus between two devices such as between a digital computer and a peripheral device, e.g. a disk drive or a tape drive. For example, digital data buses and protocols have been developed in which one device, e.g. the digital computer or a portion of the digital computer identified variously by the terms channel or controller, is permanently assigned control of the data bus for transfers of data both to and from the peripheral device. For this type of bus, frequently the device that controls the bus is referred to as the bus master and the other devices connected to the bus are referred to as slaves. Other digital data buses and protocols have been developed in which a bus arbitration circuit separate from all peripheral devices assigns control of the data bus to one or the other of two intercommunicating devices, e.g. either the digital computer or the peripheral device. This type of bus protocol is often called multi-master with centralized arbitration.
A widely used digital data bus having a sophisticated protocol for exchanging data between devices is defined by the American National Standards Institute ("ANSI") X3.131-1986 standard which is incorporated herein by reference. This ANSI standard digital data bus is known colloquially as the Small Computer System Interface ("SCSI") bus. The SCSI bus differs from most prior data buses in several ways. First, devices connect to the SCSI bus in such a way that none of the signal lines in the bus pass through any circuitry in any devices. Rather, each device applies its signals to each of the SCSI bus signal lines. The other devices then receive those signals via the bus. Second, the SCSI bus permits distributed arbitration in which all the devices that arbitrate for the bus at a particular time resolve among themselves which of them will receive control of the bus. This contrasts with the multi-master bus with centralized arbitration.
As defined by the ANSI standard, the SCSI bus includes a DATA BUS having eight bidirectional data signal lines and an optional bidirectional data parity signal line, a termination power line, ground lines, and a set of nine (9) control signal lines, some of which are bidirectional. The 9 control signal lines of the SCSI bus are a Busy ("BSY") signal line, a Select ("SEL") signal line, a Control/Data ("C/D") signal line, an Input/Output ("I/O") signal line, a Message ("MSG") signal line, a Request ("REQ") signal line, an Acknowledge ("ACK") signal line, an Attention ("ATN") signal line, and a Reset ("RST") signal line. Examples of the signals that may be transmitted over these various signal lines are illustrated in FIG. 1.
In designing devices to be interconnected by a SCSI bus, one of two mutually incompatible conventions may be selected for the electrical signals present on the bus. These two alternative electrical conventions are respectively identified as "single-ended," which has a maximum total cable length of 6 meters, and "differential," which has a maximum total cable length of 25 meters. Devices having a single-ended SCSI bus interface circuit and those having a differential SCSI bus interface circuit cannot be simultaneously connected to the same SCSI bus. Accordingly, all devices connected to a particular SCSI bus must be either single-ended or differential. The signal protocol for transferring signals over a SCSI bus remains the same regardless of which of these two, mutually exclusive electrical conventions is chosen to implement the bus.
In accordance with the ANSI SCSI bus standard for the single-ended convention, the control, data and parity signal lines in the buses are true or asserted when in their low voltage state and are false or negated when in their high voltage state. For the differential convention, assertion is the condition in which the voltage on a "-" signal line is lower than that on the associated "+" signal line. Negation reverses this relationship with the voltage on the "-" signal line becoming higher than that on the "+" signal line. In the description that follows, when a device is said to "assert" ("negate") name(s) of signal line(s), this means the device asserts (negates) the signal(s) it applies to that line (those lines) in the SCSI bus.
In both of these conventions, two termination resistor networks, positioned at opposite ends of the bus and connected to all the SCSI bus signal lines, bias them to their unasserted state when no signal is present on the line. Consequently, all the signal lines respectively remain in their unasserted state unless a device connected to the SCSI bus asserts one or more of them. Furthermore, the BSY and RST signal lines of the SCSI bus, which are "wire-OR" signal lines, may be driven simultaneously by more than one device connected to the bus. Thus, for the BSY and RST signal lines, negation by a device does not mean that the BSY or RST line is actually negated. Rather negation by a device means merely that the device ceases to assert the signal it applies to the BSY or RST line.
Each device connected to a SCSI bus is assigned a unique address on the bus. A device's address on the SCSI bus corresponds to one of the bus' eight DATA BUS signal lines. Thus, a maximum of eight devices, each device being assigned one of the device addresses 0 through 7, may be connected to a SCSI bus with the address of each such device corresponding to one of the eight DATA BUS' signal lines. In the description which follows, when a device is said to assert an address on the SCSI bus, this means that it asserts the signal on the DATA BUS line corresponding to that address.
When two SCSI devices communicate over the bus, one device acts an initiator of the exchange and the other acts as its target device. An initiating device sends commands to a target and the target device performs them. Particular devices, e.g. a digital computer, a disk drive, a tape drive, etc., usually have fixed roles as either an initiator or as a target. However, in accordance with the SCSI standard, under certain circumstances some devices may be able to selectively operate either as an initiator or as a target. Furthermore, an initiator and a target may, by mutual agreement, execute a command by having the target release the bus following receipt of the command but before completing it. Under such circumstances, the target subsequently arbitrates for the bus and then reselects the initiator to complete execution of the command.
Certain SCSI bus functions are assigned to the initiator and certain are assigned to the target. An initiator may contend for control of the SCSI bus and upon acquiring control select a particular target, or conversely. After selection or reselection has occurred, the target always controls the exchange of data from the initiator. A target may request the transfer from the initiator of COMMAND, DATA, STATUS or other information over the DATA BUS lines.
Information transfers over the data lines of the SCSI bus are interlocked and follow a defined REQ/ACK handshake protocol. One byte of information may be transferred with each REQ/ACK handshake. There are two modes of interlocking that may be selected. In an "asynchronous" mode, the transfer of each byte of data must be acknowledged before the next byte may be transferred. In a "synchronous" mode, up to eight bytes of data may be transferred before an acknowledgement must occur.
Under the signaling protocol for communicating over the SCSI bus, there are eight distinct phases: a BUS FREE phase, an ARBITRATION phase, a SELECTION phase, a RESELECTION phase, and four different information exchange phases, i.e. a COMMAND phase, a DATA phase, a STATUS phase, and a MESSAGE phase. Under the ANSI standard, some of the protocols for these 4 information exchange phases may operate in various different ways depending upon the options that have been chosen from the SCSI standard in designing the two communicating devices.
FIG. 1 depicts the signals present on the nine control signal lines and the DATA BUS signal lines in the SCSI bus. As illustrated in FIG. 1, the BUS FREE phase of SCSI bus operation, depicted to the left of dashed line 20 and to the right of dashed line 22, occurs when no device asserts either SEL or BSY. Once the BUS FREE phase of the SCSI protocol occurs, under the ANSI standard any device connected to the bus may commence activity on the bus by moving from the BUS FREE phase to the ARBITRATION phase, depicted between dashed line 20 and dashed line 24.
As illustrated between the dashed lines 20 and 24 in FIG. 1, the ARBITRATION phase of the SCSI protocol begins when one or more devices arbitrate for the bus by simultaneously asserting BSY and its address on the SCSI bus. The address asserted by each device during the ARBITRATION phase indicates that device's priority to all other devices on the bus. If a device's address on the DATA BUS corresponds to data bit 7, then that device has the highest priority on the SCSI bus. Conversely, if a device's address on the SCSI bus corresponds to data bit 0, then that device has the lowest priority on the SCSI bus.
During the ARBITRATION phase depicted between dashed lines 20 and 24, each arbitrating device checks the other DATA BUS lines to determine if any higher priority device, i.e. a device that has a higher bus address, is also concurrently arbitrating for the bus. If an arbitrating device detects that a higher priority device is also arbitrating, it then ceases participating in the arbitration by negating its BSY and address signals. If a device ceases to arbitrate, it will not again attempt to arbitrate until the bus returns to its BUS FREE phase. Conversely, if an arbitrating device detects that its address on the DATA BUS- provides it with the highest priority among the arbitrating devices, i.e. the device won the arbitration, it then completes the ARBITRATION phase by asserting SEL followed by the address of the device with which it wishes to communicate.
The SELECTION phase of the SCSI bus protocol, depicted between dashed line 24 and dashed line 26 in FIG. 1, follows immediately after an ARBITRATION phase. In the SELECTION phase, the winning device negates I/O, asserts both its and the target's addresses on the DATA BUS and then negates BSY which it has continuously asserted since the beginning of the ARBITRATION phase. Each device connected to the SCSI bus that is capable of being selected recognizes that the SELECTION phase is under way and checks its address line to determine if it is being selected. The selected device responds to selection by asserting BSY. Upon receiving the assertion of the BSY signal from the selected device, the winning arbitrating device ends the SELECTION phase by negating SEL and the addresses. At the end of the SELECTION phase, since the winning arbitrating device negated I/O during SELECTION it enters the information exchange phase(s) as the SCSI bus initiator.
Alternatively, the RESELECTION phase of the SCSI bus protocol may follow immediately after an ARBITRATION phase. The RESELECTION phase resembles the SELECTION phase except that the winning arbitrating device also asserts I/O along with the selected device's address. After the selected device asserts BSY, the winning arbitrating device reasserts BSY and then negates SEL and the addresses. After the winning arbitrating device negates SEL and the addresses, the selected device negates BSY leaving the winning arbitrating device alone asserting BSY. At the end of the RESELECTION phase, since the winning arbitrating device asserted I/O during RESELECTION it enters the information exchange phase(s) as the SCSI bus target.
Under the ANSI standard, the SCSI bus protocol need not include an ARBITRATION phase. The standard for the SCSI bus permits systems in which a sole initiating device connected to the bus moves directly from the BUS FREE phase to the SELECTION phase without ever entering the ARBITRATION phase. However, in the more sophisticated implementations of the SCSI bus allowed under the ANSI standard, devices move from the BUS FREE phase to the ARBITRATION phase before entering either the SELECTION or RESELECTION phase.
After the SELECTION phase of the SCSI bus protocol ends, the information exchange phases begin with the bus coming under the control of the target device. In the example depicted in FIG. 1, the target device initiates a COMMAND phase between dashed line 26 and dashed line 28. This COMMAND phase is followed by a DATA phase with the data being transferred from the target to the initiator between dashed line 28 and dashed line 32 in FIG. 1. The DATA phase may be followed by a STATUS phase as illustrated in FIG. 1 between dashed line 32 and dashed line 34. Finally, the STATUS phase may be followed by a MESSAGE phase with the message being transferred from the target to the initiator between dashed line 34 and dashed line 22. The SCSI standard does not established any order or number of phases associated with an information exchange. Accordingly, as many COMMAND, DATA, STATUS and/or MESSAGE phases may occur as are needed to perform the desired operation. When the target device completes the desired operation and is finished with the bus, it ends the information exchange phases by negating the signal that it is applying to the BSY signal line as illustrated at dashed line 22 in FIG. 1. Negation of the signal on the BSY signal line by the target device returns the bus once again to the BUSS FREE phase.
For economic and other reasons, it frequently is desirable to share a peripheral device such as a tape drive or a disk drive among a number of computer systems without physically altering the cable connections to those systems, and without disturbing the operation of those systems. Accordingly, for many years various manufacturers have sold devices that allow a computer system operator to electronically switch a shared peripheral device from one computer system to another. Perhaps this practice of sharing a single peripheral device among several computer systems occurs most frequently in the instance of tape drives used for backing-up onto magnetic tape the data which is stored on disk drives.
While, conceptually, an electronic switch used to share a peripheral device among two or more computer systems does not seem very complicated, usually it is not so simple as a large, passive multi-pole mechanical switch that connects to the buses of each of the sharing computer systems and to the shared peripheral device. Such a large, passive multi-pole mechanical switch is usually incompatible with the electrical characteristics of high data transfer rate buses that connect peripheral devices to a computer system. This electrical incompatibility occurs because of the simultaneous presence of high frequency signals on all of the signal lines in the buses connected to the switch and because of the isolation required between the signals on all those buses. Even in its simplest form, an electronic switch for selectively connecting a single peripheral device such as a tape drive or a disk drive to one of the buses of several computer systems is an active electronic device that provides proper electrical termination for signal lines in the several buses while isolating all the signal lines in those buses from each other except for the signal lines in the pair of buses between which signals are to be exchanged.
Thus far, bus switches for arbitration type buses exist only for multi-master centralized arbitration buses. In such central arbitration, requests for access to the bus come to a single arbitration circuit. These requests to the arbitration circuit may be presented on several different bus request signal lines that respectively correspond to different priority levels for the requesting devices. Multiple devices may be connected to the same wire-OR bus request signal line. When such bus request signals arrive at the central arbitration circuit, it decides when and to which priority level it will grant control of the bus. The result of the arbitration circuit's decision is then transmitted back to the devices via bus grant signal lines included in the bus. In these central arbitration buses, the bus grant signal lines are often daisy-chained through the devices connected to the bus so the first requesting device at a particular priority level can block retransmission of the grant signal to devices further along the bus from the central arbitration circuit, and thereby take control of the bus. This daisy-chaining and grant blocking, if present, is sometimes described a positional priority system.
With these central arbitration buses, since the bus request signals flow to the central arbitration circuit and the bus grant signals flow from that circuit, it is relatively straight forward to build a bus switch that passes them between one of several sharing buses and the shared bus. By sensing whether the bus request signal and the bus grant signal pass through the switch, it can determine the proper direction to drive the bus control lines. Moreover, by sensing which of the two interconnected buses produces the data strobe signal and whether a read or write is occurring, the bus switch can decide in which direction to drive the data lines.
Conversely, in a distributed arbitration digital data bus such as the SCSI bus, there is no central arbitration circuit. Instead, all devices are connected to the SCSI bus in parallel. Accordingly, there are no unidirectional request and grant lines from which the bus switch can sense the direction of signal transmission. Instead, the digital computing devices simultaneously contending for access to the SCSI bus decide among themselves which one is to receive access. The winning device of this arbitration then selects the device with which it will exchange data. Thus, a bus switch for the SCSI bus must appear to pass all of the bus signals freely in both directions as though it were a continuous cable while secretly determining the direction in which signals are truly passing. Furthermore, the bus switch's circuits must perform this bidirectional signal transfer imperceptibly and without introducing electrical disturbances (glitches) on the signal lines. Only with this type of signal transmission will devices on both sides of the bus switch that are competing for access to the bus be unaffected by the switch's presence between them. If the electronic circuits included in the switch are incapable of operating in this manner, signaling errors may occur.
For some interval of time, a firm named Rancho Technology has offered a SCSI bus repeater that interfaces between a single-ended SCSI bus and a differential SCSI bus. For each of the eighteen signal lines in a single-ended SCSI bus (or equivalently, for each of the eighteen pairs of signal lines in a differential SCSI bus), the Rancho Technology repeater appears to include a pair of two input NOR gates having resistors that respectively cross-couple the output signal from each of the NOR gates to an input of the other NOR gate. For each of the eighteen pairs of NOR gates, this device also appears to include capacitors connected between circuit ground and the junction between the resistors and the input of each NOR gate. In addition to the resistors and capacitors connected to one input of the NOR gates, the second input of one NOR gate in each of the eighteen pairs appears to receive the signal on one of the single-ended SCSI bus's data lines via a single-ended receiving buffer. The second input of the other NOR gate in each of the eighteen pairs appears to receive a single-ended output signal from a receiving buffer for the corresponding differential SCSI bus signal. The output signal from the NOR gate that receives the single-ended SCSI bus' signal appears to be connected to the control input of a transmitting buffer for the differential SCSI bus. The two outputs from this transmitting buffer appear to be connected in parallel to the inputs of the buffer that receives the differential SCSI bus signal. The input signal to this transmitting buffer for the differential SCSI bus appears to be the single ended SCSI bus signal that is applied to the NOR gate whose output signal appears to control the buffer's operation. The output signal from the other NOR gate that receives one of its input signals from the differential SCSI bus is applied through a NAND gate to the single-ended SCSI bus signal line and thereby is also applied to the input of the single-ended bus' receiving buffer.
The NOR gates in the circuit described above for the Rancho Technology single-ended SCSI bus to differential SCSI bus repeater appear to operate as an arbitration-latch that gives control of each of the SCSI bus' eighteen signal lines to the individual line in each bus which first asserts the signal on that line. If the circuit operates in this way, then the combined resistors and capacitors connected to the inputs of the eighteen pairs of NOR gates appear to delay latching of the cross-coupled NOR gates for a brief interval after assertion of that signal on either the single-ended or differential SCSI bus. However, the circuit for each of the eighteen SCSI bus signal lines in the Rancho Technology repeater appears to be asymmetric by its inclusion of a diode connected in parallel with one of the cross-coupling resistors. This diode has its anode connected to the output of the NOR gate that receives the single-ended SCSI bus' signal and its cathode connected to the junction of the resistor and capacitor connected to the input of the NOR gate which receives the signal from the differential SCSI bus. If the arbitration-latch in the Rancho Technology repeater operates as described above, then this diode biases the arbitration-latch's operation to provide faster response to assertion of a SCSI bus signal on the single-ended bus than assertion of that same signal on the differential bus.
Reports regarding the operation of the Rancho Technology SCSI bus repeater indicate that its eighteen relatively simple circuits, all of which operate independently of each other (e.g. there is no coupling of signal state on the SCSI bus' BSY signal line to its SEL, DB0-DB7, or DBP signal lines), does not operate reliably under all circumstances. It appears that for some SCSI bus applications the Rancho Technology single-ended to differential SCSI bus repeater operates satisfactorily and for other applications it operates unsatisfactorily. It appears reasonable to infer that the inconsistent operation of the Rancho Technology SCSI bus repeater is in some unknown way due to the simpleness of its circuit when that circuit is required to respond to signals from SCSI bus devices that employ sophisticated features of the SCSI bus protocol, e.g. reselection. It further appears that this repeater may have been designed to operate properly in SCSI systems in which arbitrating devices connect only to the single-ended bus.